STR3-440P

STR3-440P

Calibration artifact: 44nm step height, 3µm pitch

  • Calibration artifact: 44nm step height, 3µm pitch. This VLSI Surface Topography Reference Dies have a variety of Step heights and Pitchs for daily monitoring of SPM performance. The silicon die with patterned layer of SiO2 is coated with Pt. All die are 8mm x 8mm and unmounted. They are not certified or traceable to NIST.
  • This VLSI Surface Topography Reference Dies have a variety of Step heights and Pitchs for daily monitoring of SPM performance.The silicon die with patterned layer of SiO2 is coated with Pt. All die are 8mm x 8mm and unmounted. They are not certified or tr