Calibration artifact, 180nm step height, 10µm pitch. This VLSI Surface Topography Reference Dies have a variety of step heights and pitches for daily monitoring of SPM performance. The silicon die with patterned layer of SiO2 is coated with Pt. All die are 8mm x 8mm and unmounted. They are not certified or traceable to NIST. Part has been obsoleted and replaced by modelVGRP-UM.
This VLSI Surface Topography Reference Dies have a variety of Step heights and Pitchs for daily monitoring of SPM performance. The silicon die with a patterned layer of SiO2 is coated with Pt. All die are 8mm x 8mm and unmounted. They are not certified or
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